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TRF7970A
www.ti.com
SLOS743K – AUGUST 2011 – REVISED APRIL 2014
6.10 TRF7970A IC Communication Interface
6.10.1 General Introduction
The communication interface to the reader can be configured in two ways: with a eight line parallel
interface (D0:D7) plus DATA_CLK, or with a three or four wire Serial Peripheral Interface (SPI). The SPI
interface uses traditional Master Out/Slave In (MOSI), Master In/Slave Out (MISO), IRQ, and DATA_CLK
lines. The SPI can be operated with or without using the Slave Select line.
These communication modes are mutually exclusive; that is, only one mode can be used at a time in the
application.
When the SPI interface is selected, the unused I/O_2, I/O_1, and I/O_0 pins must be hard-wired as shown
in Table 6-10 . At power up, the TRF7970A samples the status of these three pins and then enters one of
the possible SPI modes.
The TRF7970A always behaves as the slave device, and the microcontroller (MCU) behaves as the
master device. The MCU initiates all communications with the TRF7970A, and the TRF7970A makes use
of the Interrupt Request (IRQ) pin in both parallel and SPI modes to prompt the MCU for servicing
attention.
Table 6-10. Pin Assignment in Parallel and Serial Interface Connection or Direct Mode
Pin
DATA_ CLK
Parallel
DATA_CLK
Parallel (Direct Mode)
DATA_CLK
SPI With SS
DATA_CLK from master
SPI Without SS (1)
DATA_CLK from master
I/O_7
A/D[7]
(not used)
MOSI
(2)
= data in (reader in)
MOSI (2) = data in (reader in)
I/O_6
A/D[6]
Direct mode, data out (subcarrier
or bit stream)
MISO (3) = data out (MCU out)
MISO (3) = data out (MCU out)
I/O_5 (4)
A/D[5]
Direct mode, strobe – bit clock
out
See
(4)
See
(4)
I/O_4
I/O_3
I/O_2
I/O_1
I/O_0
IRQ
A/D[4]
A/D[3]
A/D[2]
A/D[1]
A/D[0]
IRQ interrupt
(not used)
(not used)
(not used)
(not used)
(not used)
IRQ interrupt
SS – slave select (5)
(not used)
At VDD
At VDD
At V SS
IRQ interrupt
(not used)
(not used)
At VDD
At V SS
At V SS
IRQ interrupt
(1)
(2)
(3)
(4)
(5)
FIFO is not accessible in SPI without SS mode. See device errata for detailed information.
MOSI = Master Out, Slave In
MISO = Master In, Slave Out
I/O_5 pin is used only for information when data is put out of the chip (for example, reading 1 byte from the chip). It is necessary first to
write in the address of the register (8 clocks) and then to generate another 8 clocks for reading out the data. The I/O_5 pin goes high
during the second 8 clocks. But for normal SPI operations, I/O_5 pin is not used.
Slave_Select pin is active low
Copyright ? 2011–2014, Texas Instruments Incorporated
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